The present invention relates to CMOS devices.
Latch-up has been a chronic problem in the CMOS art, and is predicted to become a much greater problem as CMOS devices are reduced to smaller and smaller dimensions. Latch-up results from the operation of a parasitic bipolar device, i.e. a bipolar device which is not intentionally designed as part of the circuit, but which in fact results from the device structures as fabricated. For example, in N-well CMOS technology, an N+ source/drain region and a P+ source/drain region will be separated by a portion of the N-well and of the P-substrate. This NPNP device can be considered as a thyristor, and, with the small device spacing which is preferable for integrated circuits, this NPNP device will in fact fire as a thyristor at levels of injection current which may easily be achieved. Thus, any time a large potential difference exists between neighboring N+ and P+ regions, the parasitic thyristor may turn on and pass very large currents, which may cause a stuck logic condition or may destroy the CMOS device. This condition is known as latch-up.
The prior art has sought to reduce the gain of the parasitic thyristor or to avoid its ever getting a sufficient injection current to turn on. However, the present invention avoids latch-up in a new way: in the present invention, the parasitic thyristor does not exist, since the N-channel and P-channel devices are not both fabricated in the substrate.
That is, in the present invention one device type (preferably the PMOS) is fabricated as SOI devices rather than as bulk devices. This means that the NMOS and PMOS devices do not in general share this same substrate. Thus, although a diode may exist where the P+ regions butt up against the N+ regions, there is no current path for a thyristor structure to exist.
In particular, in the presently preferred embodiment, well implants into the bulk are not necesssary. Thus it is possible to use the P+ and N+ regions as conductors, and a P+ to N+ contact requires only a merged contact with a spot of metal to bridge the P+ to N+ diode. Since thyristor action is prevented, and PMOS and NMOS devices can be placed closer together higher total density results.
According to the present invention there is provided:
A CMOS integrated circuit, comprising:
a monolithic semiconducting substrate; PA2 a plurality of N-channel insulated-gate-field-effect transistors formed in said substrate; PA2 a plurality of P-channel silicon-on-insulator insulated-gate-field-effect transistors formed atop said substrate; and PA2 means for interconnecting said N-channel and P-channel transistors to embody a predetermined circuit function.